A Multichannel, High-Bandwidth Wirelane Receiver for D2D Interconnects

This paper proposes a multichannel and high-bandwidth (BW) receiver for standard packaging die-to-die (D2D) interconnects. The adopts forward clock (FCK) architecture of the high-density transmission standard, which consists 16 high-speed data paths pair low-speed differential clocks 512 Gbps BW. To reduce chip area power consumption, common minimal phase-locked loop (MINI-PLL) adjustment (CDA) circuit to replaces recovery (CDR) in traditional receiver. A delay-matching is adopted combat PVT variation lane skew. In addition, high linearity phase interpolator (PI) design used minimum adjust improve jitter performance. Using 28 nm CMOS technology, overall link consumption 1.56 pJ/b. Bit error rate (BER) less than 10−15 under real S-parameters with channel loss 10db@16GHz.